Future works

Some future works that will be faced in the future could be:

Noise problems

-- This means to use another target in the optimization policies: the ``noise'' ([18]) of a circuit.
This is a complex field, and a good starting point could be developing of a noise-model of a CMOS circuit.

Interconnections

-- A simpler work could be to take into account the influence of interconnections in the optimization.
This means both to include a model of the interconnections into the cell and to optimize the performance of the whole structure.

Topology extensions

-- The optimizer can be expanded to perform the optimization of different structures from the standard cells (both static and dynamic): for example the memory cells, or the pass-logic gates.
This means principally to modify the algorithm that performs the automatic search of all the critical paths in a circuits, to adapt it to different topologies. There is, anyway, the possibility in the optimizer to list the critical path by hand and to perform the optimization with these paths.

Cad integration

-- The optimizer could be integrated in a standard CAD tool that assists the designer in developing an ASIC from high-level specifications to layout level. One step of this flow could be the optimization of the library employed in the project.