Conclusions

The goal of the optimization framework presented in this chapter is to show a new way to optimize the performance of CMOS cells employed in VLSI circuits.
This new methodology, the multi-objective optimization, has led to a prominent result: the delay of a circuit can be reduced taking into account the power consumption and the area occupancy. The results of table 7.6 are the most effective: giving a small compromise of the delay performance with respect of a full delay optimization, the power consumption is strongly decreased; this means that the default optimization done until nowadays, the full delay optimization, can be safely switched with a multi-objective optimization. A circuit that has less power consumption while maintaining almost the same delay is safer from the operating point of view: it develops less heat, hence it is more reliable.

The easiness of obtaining circuits in which several optimization policies can be performed helps a lot the work of cell-library designer: the designer can, with a very low effort, produce with the same version of a library several libraries optimized in different ways. So each cell in a library has different performances with respect to the same cell in the other libraries, but it is still fully equivalent by the point of view of the function performed. Let's think for example to an ``and'' gate that performs always the same function, but with different delays or maybe different power dissipations.
Simply swapping one library version (for example one optimized only for the delay) with another (for example one optimized taking into account the power consumption), the designer can develop several versions of the same project with different performances.