Optimization

The cell library to be optimized is composed, principally, by basic TSPC³ CMOS dynamic logic, but with the purpose to extend the validity of the results, some static gates are included in the library. The full list of the gates subjected to optimization is shown in table 7.1. For a complexity description (both for the number of transistor in each cell, and for the number of critical paths in the same cell) of the gates see table 5.1 (page ).

Table 7.1: Library gates list

Gate

Inverter (fig. 5.10, page )

TSPC type n latch (fig. 5.11(a), page )

TSPC type p latch (fig. 5.11(b), page )

TSPC type n and (fig. 5.12(a), page )

TSPC type p and (fig. 5.12(b), page )

TSPC type n or (fig. 5.13(a), page )

TSPC type p or (fig. 5.13(b), page )

Static and-or (fig. 5.14, page )

Static and (fig. 5.14, page ) (See note 14, page .)

Static or (fig. 5.14, page ) (See note 14, page .)

Static parity gate (fig. 5.15, page )

Static full-adder (figs. 5.16(a), 5.16(b), page )

TSPC full-adder (one-stage) (figs. 5.17(a), 5.17(b), page )

TSPC full-adder (basic cells)

Figure: Comparison of $0.7\,\mathrm{\mu m}$ and $0.25\,\mathrm{\mu m.}$ gates @ minimum technology width

[Delay] [Energy-dissipation]

The library comprehends, thus, the inverter gate, the TSPC gates ``and'' (both the n and the p versions), ``or'' and ``latch'' gates (again with the n and the p versions), and a full-adder (the version included here is a n-p construction, faster than the almost equivalent p-n construction). As above said, for comparison are included: a complete static full-adder, a full static ``and-or'' gate⁴, a full static ``and'', a full static ``or'', a full static ``parity'' gate (which performs the parity calculation among three inputs), and, finally, a TSPC full-adder, composed only by the TSPC basic gates above mentioned.

The very first result reported here is the comparison of the improvement in the delay and power consumption between the $0.7\,\mathrm{\mu m}$ and the $0.25\,\mathrm{\mu m}$ technology, at minimum width: this comparison is reported in table 7.2 and graphically pitted in figure 7.1(a) for delay and figure 7.1(b) for the power consumption.

From that table it is possible to see that the average improvement (diminution) of the delay is $69.3\%$ and of the power is $76.2\%$, passing from the $0.7\,\mathrm{\mu m}$ to the $0.25\,\mathrm{\mu m}$ technology.
Thus with scaling the dimension of quite $\tfrac{1}{3}$, the average delay and power consumption are also scaled down of about the same factor.