CMOS logic families

The first basic distinction inside the CMOS logic families is among the static logics and the dynamic logics ([1]).

Static logic:

The static logic is a logic in which the functioning of the circuit is not synchronized by a global signal, namely the clock of the circuit. The output is solely function of the input of the circuit, and it is asynchronous with respect to them. The timing of the circuit is defined exclusively by its internal delay.

Dynamic logic:

The dynamic logic is a logic in which the output is synchronized by a global signal, viz. the clock. The output is, then, function both of the inputs of the circuit and of the clock signal; and the timing of the circuit is defined both by its internal delay and by the timing of the clock.

Both the static and dynamic logics comprehend several logic families.