Introduction

We might ask: why to optimize a single cell in VLSI circuit, when the design nowadays is shifting toward higher and higher level?

Some answers could be:

• Need of re-usable library cells. This makes easier to reuse the same library for different projects. It is a must nowadays, in order to reduce the total time to target/market.
• An optimized library makes easier the design at higher level: floor-planning, routing, can have ``relaxed'' constraints, since the gates have a better ``behaviour''. It is possible to reduce the time to repeat some critical steps like floorplanning or routing until all the specifications are met: these specifications are met earlier, since the cell globally have a better behaviour.
• Need of having some equivalent libraries with different kind of optimization. It is possible to have different libraries that have different specifications, but are functionally equivalent, so that it is possible to create different version of a project simply substituting the basic library. It would be possible, for example, to have, of the same project, a version that runs at full speed, and version optimized for low-power dissipation.
  This swapping of libraries does not involve the higher levels of design, for it is totally transparent to the designer during floorplanning or routing. Just before the layout production, during the cell mapping, it is possible to choose the library on to which the project would be mapped.

These answer have led to consider the appropriateness of the production of a tool able to perform the optimization of a cell library, in a way appropriate for the designer. The goal is to produce some results to show that this optimization is worth during a design cycle, and also to make the insertion of the tool in a design cycle as smooth as possible.

In order to attain results that are related to a real production cycle, we have to choose some cells that are almost present in a real library.
For this purpose we introduce a very brief description of the most used CMOS logic families, and among them we choose the cells to develop and test the optimization framework.