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The design of high speed integrated circuit is a long and complex operation; nonetheless the total time-to-market required from the idea to the silicon masks is reducing along the way.
To help the designer during this long and winding road several CAD tools are available. In the first step the only thing existing is the description of the circuit behaviour (the ``idea''); in the central step of the design flow the designer knows only the logic functioning of each block composing the circuit, but he ignores the technology realization of these blocks; in the last steps, finally, the designer knows exactly the technology implementation of every single gate of the circuit, and can ``compose'' the final layout with every gate. Ca va sans dire that the CAD tool are nowadays of vital importance in the design flow, and moreover the goodness or the badness of such tools influence a lot the quality of the final design.

Among all the possible instruments, the optimization tools have a primary role in all the phases of a project, starting from the optimization at higher level and descending to the optimization made at the electrical level.

This thesis focuses its efforts in developing new strategies and new techniques for the optimization made at the transistor dimension level, that is the one done by the cell library engineer, and developing also a CAD instrument to make this work as more as harmless as possible.