Results

Figure 3.9: Delay of the circuit 3.2 with several combination of $W_1$ and $W_2$.

[FAST model] [HSPICE]

The circuit in figure 3.2 with 2 n-MOS and 2 p-MOS transistors (in a $0.7\,\mathrm{\mu m}$ technology) has been simulated using HSPICE (level 6) and the proposed model, for each combination of MOSFET widths from 1  $\mathrm{\mu m}$ to 100  $\mathrm{\mu m}$. Figure 3.9 shows the comparison between delay (defined as the delay at 50% between an input rise ramp of 200 ps and an output falling ramp) calculated by the model and the delay simulated by HSPICE for each combination of widths among 5  $\mathrm{\mu m}$ and 30  $\mathrm{\mu m}$; similarly figure 3.10 shows the comparison between the energy dissipated (during the output discharging) by the circuit calculated by the model and by HSPICE.

Figure 3.10: Energy dissipated by the circuit of figure 3.2 with several combination of $W_1$ and $W_2$

[FAST model] [HSPICE]

Table 3.1: Mean Error

	Mean error	Max Error	Min Error
Delay	6.115%	12.985 %	0.905%
Energy dissipated	2.1%	6.3%	0.11%

Table 3.2: Execution time

HSPICE execution time	FAST execution time
6384.3 sec.	188.91 sec.

The errors between the proposed model and the HSPICE simulation is reported in table 3.1 while table 3.2 shows corresponding execution time. These results are taken from the analysis of the circuit varying the dimensions of the MOSFETs continuously from 1  $\mathrm{\mu m}$ to 100  $\mathrm{\mu m}$.