List of Figures

1. Static and
2. Pass-transistor logic xor
3. Domino typical gate
4. CVSL typical gate
5. CMOS typical gate
6. TSPC Latches
7. $RC$ MOS equivalence
8. $RC$ chain
9. $RC$ single cell
10. Elmore impulse response
11. Inverter voltages waveform
12. Mos chain
13. Node voltages
14. Voltages wave form in the n-MOS chain
15. Voltages wave forms in the p-MOS chain
16. $V_{DS}$ and $V_{GS}$
17. MOSFET chain with static voltages
18. Threshold variation
19. Delay comparison
20. Energy comparison
21. Section search
22. Minimization by Powell algorithm
23. Minimization by Powell algorithm
24. Minimization by SLOP algorithm
25. Minimization by Simulated-annealing algorithm
26. Minimization by Simulated-annealing algorithm
27. Design flow
28. Delay definition
29. Critical paths
30. Critical path tree
31. Elmore delay
32. Elmore delay
33. HSPICE delay
34. FAST delay
35. HSPICE Energy
36. CMOS Inverter
37. TSPC Latches
38. TSPC And gates
39. TSPC Or gates
40. Static parity gate
41. Tool block diagram
42. Comparison of $0.7\,\mathrm{\mu m}$ and $0.25\,\mathrm{\mu m.}$ gates @ minimum technology width
43. Delay optimization of $0.7\,\mathrm{\mu m}$ gates.
44. Delay optimization of $0.25\,\mathrm{\mu m}$ gates.
45. Technology comparison of delay optimization.
46. Several delay-power optimization policies of $0.7\,\mathrm{\mu m}$ gates.
47. Energy-dissipation variation (zoom of figure 7.5(b))
48. Several delay-power optimization policies of $0.25\,\mathrm{\mu m}$ gates.
49. Energy-dissipation variation (zoom of figure 7.7(b))
50. Delay-power optimization ($50\%$-$50\%$) comparison of $0.7\,\mathrm{\mu m}$ and $0.25\,\mathrm{\mu m}$ gates.
51. Delay and power trajectory during 4 different multi-objective optimizations for the and-or gate
52. Delay and power trajectory during 4 different multi-objective optimizations for the parity gate
53. Delay and power trajectory during 4 different multi-objective optimizations for the static full-adder
54. Delay and power trajectory during 4 different multi-objective optimizations for the dynamic full-adder