Dynamic logic families

The principal dynamic families have a characteristic in common: every dynamic logic needs of a pre-charge (or pre-discharge) transistor to lead to a known state some pre-charged nodes. This is done during the working phase known as pre-charge phase or memory phase; during another working phase, the evaluation phase the output has a stable value.

The principal dynamic logics are divided yet in two sub-families, pipelined and not-pipelined. The first two these are non-pipelined, while the others are pipelined:

Domino logic and N-P Domino logic

The typical domino gate is depicted in figure 1.3

Figure 1.3: Domino typical gate

During the pre-charge phase the clock is at its low state, so that the pre-charged node before the static inverter is high, and the output is low. During the evaluation phase the clock is high, so that the inputs of the n-block (that can perform any logical function) can discharge the pre-charged node and lead the output to the high state.

We can cascade several of these gates, given that each gate has its own output inverter, and we can drive every gate with the same clock signal, given that the evaluation phase lasts the time necessary to all the gates to finish their inputs evaluation. This last fact explains why this is a non-pipelined logic: the output of every cell is available when the cell has finished its evaluation phase.
Moreover this logic has a limited area occupancy, since it has a low number of PMOS transistors. On the other hand it is not possible to implement inverting-structure and, as all the other dynamic logics, this logic is subject to the charge-sharing problem.

A natural evolution of the domino logic is the N-P domino logic, or zipper logic. It consist of two typical cells, the one depicted in figure 1.3, and the dual one obtained by that, simply swapping the n-block with a p-block, and a PMOS pre-charge transistor with a NMOS pre-discharge transistor, driven by the negated clock.
This logic has a lower are occupancy, since there is no need of a static inverter, but has also a lower speed, given by the presence of PMOS transistors.

Cascode voltage switch logic (CVSL)

The CVSL is part of the large family of differential logics. It needs both the inputs and the inputs negated, and two complementary n-block that perform the logic function, as it is possible to see in figure 1.4.

Figure 1.4: CVSL typical gate

It has the advantage to be quite fast, since the positive feed-back of the two PMOS accelerates the switching of the gate, and also it has very good noise margins. Moreover it produces both the outputs and negated outputs without needing an inverter. As a drawback, it has a large area occupancy.

CMOS logic

The typical CMOS gate is shown in figure 1.5. It is basically a three-state gate, since when the clock is at the low state, the output is floating at the high impedance state.

Figure 1.5: CMOS typical gate

It is principally used as a dynamic latch, as an interface among static logics and dynamic-pipelined logics.

NO RAce logic (NORA)

The NORA logic, as acronym of no race, is an evolution of the N-P domino logic. The static inverter of the domino logic is substituted with a CMOS inverter. This is the first of the pipelined logics, since the output of every gates is available only when the clock switch its state, and not before.

Since the output stage of every cell is also dynamic (a CMOS inverter), then this logic is more subject to the charge-sharing problem that the domino logic is.

True Single Phase Clock logic (TSPC)

The final evolution of the NORA is the TSPC logic, or true single phase clock logic ([2]).
The TSPC logic is a n-p logic, since of each gate exists the n-version and the p-version. For example the n-latch and the p-latch are shown in figure 1.6.

Figure 1.6: TSPC Latches

[Type n] [Type p]

The ultimate advantage of the TSPC logic is the presence of a single clock, since for its internal structure it is not necessary the presence of the clock negated.

The TSPC logic is among the faster dynamic families, and surely it has a great appealing for its very low number of transistor employed.